1. Field of the Invention
The present invention is directed in general to integrated circuit devices and methods for manufacturing same. In one aspect, the present invention relates to a capacitor formed in a semiconductor device.
2. Description of the Related Art
Integrated circuit devices, such as dynamic random access memory (DRAM) devices, increasingly require high performance capacitors with sufficient capacitance to extend the refresh period and increase tolerance to alpha particles. For example, a typical DRAM cell configuration includes a capacitor for storing a charge (i.e., the bit of information) and an access transistor that provides access to the capacitor during read and write operations. To increase the storage node capacitance for high performance memory cells relative to bit line capacitance, the overlap area between an upper electrode (plate electrode) and a lower electrode (storage node electrode) should be increased and/or the thickness of a dielectric film interposed between the upper and lower electrodes should be reduced, for example by using a high-k dielectric material having a high dielectric constant k. And while plate overlap can be increased by forming large, overlapping lateral capacitor plate layers, such structures reduce the pattern density at the memory region, resulting in loading effects during photo lithography, etch, and polishing steps. Another technique for increasing capacitance is to fabricate the capacitor in the semiconductor substrate as a cylinder-shaped electrode plate that is concentrically positioned around a lower or storage node electrode plate to create the increased capacitance from the surface area of the storage node electrode. However, the height of such cylindrical capacitors is effectively limited by the constraints from high aspect ratio contact etch limitations which prevent contact etching from proceeding to a sufficient depth. For example, aspect ratios as high as 50-60 are now common in state-of-the-art DRAM devices. While the technical difficulties of fabricating high aspect ratio cell capacitors can be eased by using separate photolithographic steps to stack several vertical layers on top of each other to eventually form one cell capacitor, such multi-stack capacitor manufacturing presents new problems with properly aligning electrodes in the different stack levels to avoid electrical shorts or gaps, and can also damage the capacitor dielectric layers which are sequentially deposited and etched in each stack level. Another approach for increasing the storage capacitance, such as shown in U.S. Pat. No. 7,449,739, is to form embedded upper and lower capacitor stacks which each include a cylindrically shaped inner storage node and an outer electrode that wraps around a thin capacitor dielectric film formed on the inner storage node. However, the fabrication of capacitor stacks requires that, at each stack, the top of the outer electrode must be recessed below the top of the inner storage node to prevent the outer electrode and inner storage node from being electrically shorted together. To achieve such recessed plate heights, one or more control liner layers may be formed over the top of the inner storage node and then carefully etched to prevent the top of the outer electrode from being exposed. As seen from the foregoing, there continue to be challenges associated with designing and fabricating high performance capacitors.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.